A New Vlsi Architecture for 2-d Dst Transform of Prime Length

Using a recently proposed VLSI algorithm for 2-D discrete sine transform (DST) an efficient VLSI architecture is proposed. This VLSI architecture has a modular and regular hardware structure and can compute in parallel thus resulting in high speed performances. The proposed architecture has been obtained by mapping the VLSI algorithm into two linear systolic arrays and combining them into a single linear systolic array having a high computing speed and low I/O cost with a small number of I/O channels placed at the two ends of the linear array. The presented architecture has all the advantages of the systolic array paradigm, like regular and modular structure with an interconnection topology appropriated for the VLSI technology.